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40-channel, 14-bit, serial input, voltage output dac ad5371 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2008 analog devices, inc. all rights reserved. features 40-channel dac in 80-lead lqfp and 100-ball csp_bga guaranteed monotonic to 14 bits maximum output voltage span of 4 v ref (20 v) nominal output voltage span of ?4 v to +8 v multiple, independent output voltage spans available system calibration function allowing user-programmable offset and gain channel grouping and addressing features thermal shutdown function dsp/microcontroller-compatible serial interface spi/lvds serial interface 2.5 v to 5.5 v digital interface digital reset ( reset ) clear function to user-defined siggndx simultaneous update of dac outputs applications level setting in automatic test equipment (ate) variable optical attenuators (voa) optical switches industrial control systems instrumentation functional block diagram 14 ad5371 vref0 siggnd0 vref2 siggnd4 siggnd3 siggnd2 vout0 vout1 vout2 vout3 vout4 vout5 vout6 vout7 vout16 to vout39 ldac dv cc v dd v ss agnd dgnd x1a register x1b register c register m register buffer group 0 spi/lvds sync sclk sync sdi sdi sclk sdo busy reset clr state machine output buffer and power-down control output buffer and power-down control dac 7 offset dac 0 dac 0 buffer ofs0 register 14 14 14 14 14 14 14 14 14 14 14 8 8 14 dac 0 register 14 dac 7 register mux 2 mux 1 mux 1 mux 1 mux 1 to mux2 a/b select register control register x1a register x1b register c register m register 14 14 14 14 x2a register x2b register 14 14 14 14 14 mux 2 vref1 vout8 vout9 vout10 vout11 vout12 vout13 vout14 vout15 x1a register x1b register c register m register buffer group 1 output buffer and power-down control output buffer and power-down control dac 7 offset dac 1 dac 0 buffer ofs1 register 14 14 14 14 14 14 14 14 14 14 14 8 8 dac 0 register 14 dac 7 register mux 2 to mux2 a/b select register x1a register x1b register c register m register 14 14 14 14 14 14 14 14 mux 2 vref2 supplies group 2 to group 4 siggnd1 group 2 to group 4 are same as group 1 x2a register x2b register 14 x2a register x2b register 14 x2a register x2b register 14 serial interface 05814-001 figure 1.
ad5371 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications..................................................................................... 4 performance specifications......................................................... 4 ac characteristics........................................................................ 5 timing characteristics ................................................................ 6 absolute maximum ratings............................................................ 9 esd caution.................................................................................. 9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 13 terminology .................................................................................... 15 theory of operation ...................................................................... 16 dac architecture....................................................................... 16 channel groups.......................................................................... 16 a/b registers and gain/offset adjustment............................ 17 load dac.................................................................................... 17 offset dacs ................................................................................ 17 output amplifier........................................................................ 18 transfer function ....................................................................... 18 reference selection .................................................................... 18 calibration................................................................................... 19 additional calibration............................................................... 19 reset function ............................................................................ 20 clear function ............................................................................ 20 busy and ldac functions...................................................... 20 power-down mode .................................................................... 20 thermal shutdown function ................................................... 20 toggle mode................................................................................ 21 serial interface ................................................................................ 22 spi interface ................................................................................ 22 lvds interface............................................................................ 22 spi write mode .......................................................................... 22 spi readback mode ................................................................... 23 lvds operation ......................................................................... 23 register update rates ................................................................ 23 channel addressing and special modes ................................. 23 special function mode.............................................................. 25 applications information .............................................................. 27 power supply decoupling ......................................................... 27 power supply sequencing ......................................................... 27 interfacing examples ................................................................. 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 3/08rev. a to rev. b added table 1.................................................................................... 3 changes to timing characteristics section.................................. 6 changes to absolute maximum ratings section......................... 9 changes to table 7.......................................................................... 11 changes to figure 16, figure 18, and figure 19 ......................... 14 changes to a/b registers and gain/offset adjustment section and load dac section .................................................... 17 changes to transfer function section......................................... 18 changes to calibration section .................................................... 19 changes to reset function section and clear function section.............................................................................................. 20 changes to table 9.......................................................................... 20 changes to register update rates section.................................. 23 11/07rev. 0 to rev. a reformatted specifications table 1 .................................................3 reformatted specifications table 2 .................................................6 change to a/b registers and gain/offset adjustment section ........................................................................ 19 change to spi write mode section.............................................. 24 changes to ordering guide .......................................................... 31 8/07revision 0: initial version
ad5371 rev. b | page 3 of 28 general description the ad5371 1 contains 40 14-bit dacs in a single 80-lead lqfp or 100-ball csp_bga. the device provides buffered voltage outputs with a span of 4 the reference voltage. the gain and offset of each dac can be independently trimmed to remove errors. for even greater flexibility, the device is divided into five groups of eight dacs. three offset dacs allow the output range of the groups to be adjusted. group 0 can be adjusted by offset dac 0, group 1 can be adjusted by offset dac 1, and group 2 to group 4 can be adjusted by offset dac 2. the ad5371 offers guaranteed operation over a wide supply range, with v ss from ?16.5 v to ?4.5 v and v dd from 9 v to 16.5 v. the output amplifier headroom requirement is 1.4 v operating with a load current of 1 ma. 1 protected by u.s. patent no. 5,969,657; other patents pending. the ad5371 has a high speed serial interface that is compatible with spi, qspi?, microwire?, and dsp interface standards and can handle clock speeds of up to 50 mhz. it also has a 100 mhz low voltage differential signaling (lvds) serial interface. the dac registers are updated on reception of new data. all the outputs can be updated simultaneously by taking the ldac input low. each channel has a programmable gain and an offset adjust register to allow removal of gain and offset errors. each dac output is gained and buffered on chip with respect to an external siggndx input. the dac outputs can also be switched to siggndx via the clr pin. table 1. high channel count bipolar dacs model resolution (bits) nominal output span output channels linearity error (lsb) ad5360 16 4 v ref (20 v) 16 4 ad5361 14 4 v ref (20 v) 16 1 ad5362 16 4 v ref (20 v) 8 4 ad5363 14 4 v ref (20 v) 8 1 ad5370 16 4 v ref (12 v) 40 4 ad5371 14 4 v ref (12 v) 40 1 ad5372 16 4 v ref (12 v) 32 4 ad5373 14 4 v ref (12 v) 32 1 ad5378 14 8.75 v 32 3 ad5379 14 8.75 v 40 3
ad5371 rev. b | page 4 of 28 specifications performance specifications dv cc = 2.5 v to 5.5 v; v dd = 9 v to 16.5 v; v ss = ?16.5 v to ?8 v; vref = 3 v; agnd = dgnd = siggndx = 0 v; c l = open circuit; r l = open circuit; gain (m), offset (c), and dac offset regist ers at default values; temperature range for the ad5371 is ?40c to +85c; all specifications t min to t max , unless otherwise noted. table 2. parameter min typ 1 max unit test conditions/comments 1 accuracy resolution 14 bits integral nonlinearity (inl) ?1 +1 lsb differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic by design zero-scale error ?10 +10 mv before calibration full-scale error ?10 +10 mv before calibration gain error 0.1 % fsr zero-scale error 2 1 lsb after calibration full-scale error 2 1 lsb after calibration span error of offset dac ?35 +35 mv see the offset dacs section for details voutx temperature coefficient (vout0 to vout39) 5 ppm fsr/c includes linearity, offset, and gain drift dc crosstalk 2 120 v typically 20 v; measured channel at midscale, full-scale change on any other channel reference inputs (vref0, vref1, vref2) 2 vrefx input current ?10 +10 a per input; typically 30 na vrefx range 2 5 v 2% for specified operation siggnd inputs (siggnd0 to siggnd4) 2 dc input impedance 50 k typically 55 k input range ?0.5 +0.5 v siggndx gain 0.995 1.005 output characteristics 2 output voltage range v ss + 1.4 v dd ? 1.4 v i load = 1 ma nominal output voltage range ?4 +8 v short-circuit current 15 ma voutx to dv cc , v dd , or v ss load current ?1 +1 ma capacitive load 2200 pf dc output impedance 0.5 digital inputs input high voltage 1.7 v dv cc = 2.5 v to 3.6 v 2.0 v dv cc = 3.6 v to 5.5 v input low voltage 0.8 v dv cc = 2.5 v to 5.5 v input current ?1 +1 a excluding clr pin clr high impedance leakage current ?20 +20 a input capacitance 2 10 pf digital outputs (sdo, busy ) output low voltage 0.5 v sinking 200 a output high voltage (sdo) dv cc ? 0.5 v sourcing 200 a sdo high impedance leakage current ?5 +5 a high impedance output capacitance 2 10 pf
ad5371 rev. b | page 5 of 28 parameter min typ 1 max unit test conditions/comments 1 lvds interface (reduced range link) digital inputs 2 input voltage range 875 1575 mv input differential threshold C0.1 +0.1 v external termination resistance 80 100 132 differential input voltage 100 mv power requirements dv cc 2.5 5.5 v v dd 9 16.5 v v ss ?16.5 ?4.5 v power supply sensitivity 2 ?full scale/?v dd ?75 db ?full scale/?v ss ?75 db ?full scale/?dv cc ?90 db di cc 2 ma dv cc = 5.5 v, v ih = dv cc , v il = gnd; normal operating conditions i dd 18 ma outputs unloaded, dac outputs = 0 v 20 ma outputs unloaded, dac outputs = full scale i ss ?18 ma outputs unloaded, dac outputs = 0 v ?20 ma outputs unloaded, dac outputs = full scale power dissipation unloaded (p) 280 mw v ss = ?8 v, v dd = 9.5 v, dv cc = 2.5 v power-down mode control register power-down bit set di cc 5 a i dd 35 a i ss ?35 a junction temperature 3 130 c t j = t a + p total ja 1 typical specifications are at 25c. 2 guaranteed by design and characterization; not production tested. 3 ja represents the package thermal impedance. ac characteristics dv cc = 2.5 v; v dd = 15 v; v ss = ?15 v; vref = 3 v; agnd = dgnd = siggndx = 0 v; c l = 200 pf; r l = 10 k; gain (m), offset (c), and dac offset registers at default values; all specifications t min to t max , unless otherwise noted. table 3. ac characteristics 1 parameter min typ max unit test conditions/comments dynamic performance output voltage settling time 20 s settl ing to 1 lsb from a full-scale change 30 s dac latch contents alternately loaded with all 0s and all 1s slew rate 1 v/s digital-to-analog glitch energy 5 nv-s glitch impulse peak amplitude 10 mv channel-to-channel isolation 100 db vref0, vref1, vref2 = 2 v p-p, 1 khz dac-to-dac crosstalk 20 nv-s digital crosstalk 0.2 nv-s digital feedthrough 0.02 nv-s effect of in put bus activity on dac output under test output noise spectral density @ 10 khz 250 nv/hz v ref = 0 v 1 guaranteed by design and characterization; not production tested.
ad5371 rev. b | page 6 of 28 timing characteristics dv cc = 2.5 v to 5.5 v; v dd = 9 v to 16.5 v; v ss = ?16.5 v to ?8 v; vrefx = 3 v; agnd = dgnd = siggndx = 0 v; c l = 200 pf to gnd; r l = open circuit; gain (m), offset (c), and dac offset registers at default values; all specifications t min to t max , unless otherwise noted. table 4. spi interface parameter 1 , 2 , 3 limit at t min , t max unit description t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 11 ns min sync falling edge to sclk falling edge setup time t 5 20 ns min minimum sync high time t 6 10 ns min 24 th sclk falling edge to sync rising edge t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 4 42 ns max sync rising edge to busy falling edge t 10 1/1.5 s typ/s max busy pulse width low (single-channel update); see table 9 t 11 600 ns max single-channel update cycle time t 12 20 ns min sync rising edge to ldac falling edge t 13 10 ns min ldac pulse width low t 14 3 s max busy rising edge to dac output response time t 15 0 ns min busy rising edge to ldac falling edge t 16 3 s max ldac falling edge to dac output response time t 17 20/30 s typ/s max dac output settling time t 18 140 ns max clr / reset pulse activation time t 19 30 ns min reset pulse width low t 20 400 s max reset time indicated by busy low t 21 270 ns min minimum sync high time in readback mode t 22 5 25 ns max sclk rising edge to sdo valid t 23 80 ns max reset rising edge to busy falling edge 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 see figure 4 and figure 5. 4 t 9 is measured with the load circuit shown in figure 2. 5 t 22 is measured with the load circuit shown in figure 3. table 5. lvds interface parameter 1 , 2 , 3 limit at t min , t max unit description t 1 12 ns min sclk cycle time t 2 5 ns min sclk pulse width high and low time t 3 5 ns min sync to sclk setup time t 4 3 ns min data setup time t 5 3 ns min data hold time t 6 3 ns min sclk to sync hold time t 7 10 ns min sync high time 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 see figure 6.
ad5371 rev. b | page 7 of 28 circuit and timing diagrams to output pin c l 50pf r l 2.2k ? v ol dv cc 05814-002 figure 2. load circuit for busy timing diagram v oh (min) ? v ol (max) 2 200a i ol 200a i oh t o output pin c l 50pf 0 5814-003 figure 3. load circuit for sdo timing diagram sclk sync sdi busy v outx 1 v outx 2 voutx reset voutx clr 1 2 24 t 8 t 12 t 10 t 13 t 17 t 14 t 15 t 13 t 17 t 9 t 7 t 5 t 4 t 2 t 6 db23 db0 t 16 1 ldac active during busy. 2 ldac active after busy. busy ldac 1 ldac 2 1 t 3 t 20 t 23 t 18 t 18 t 19 24 t 11 t 1 05814-004 figure 4. spi write timing
ad5371 rev. b | page 8 of 28 05814-005 sdi sdo 48 input word specifies register to be read nop condition selected register data clocked out t 22 t 21 lsb from previous write sclk sync db0 db0 db0 db0 db23 db23 db23 db15 figure 5. spi read timing s ync s ync t 3 t 1 t 6 t 4 t 5 t 2 msb d23 lsb d0 sclk sclk sdi sdi 0 5814-006 figure 6. lvds timing
ad5371 rev. b | page 9 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 60 ma do not cause scr latch-up. table 6. parameter rating v dd to agnd ?0.3 v to +17 v v ss to agnd ?17 v to +0.3 v dv cc to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to dv cc + 0.3 v digital outputs to dgnd ?0.3 v to dv cc + 0.3 v vref0, vref1, vref2 to agnd ?0.3 v to +5.5 v vout0 through vout39 to agnd v ss ? 0.3 v to v dd + 0.3 v siggnd0 through siggnd4 to agnd ?1 v to +1 v agnd to dgnd ?0.3 v to +0.3 v operating temperature range (t a ) industrial (b version) ?40c to +85c storage temperature range ?65c to +150c operating junction temperature (t j max) 130c ja thermal impedance 80-lead lqfp 38.72c/w 100-ball csp_bga 40c/w reflow soldering peak temperature 230c time at peak temperature 10 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5371 rev. b | page 10 of 28 pin configurations and function descriptions 2 clr 3 reset 4 busy 7 siggnd3 6 vout27 5 testi 1 8 vout28 9 vout29 10 vout30 12 vout32 13 vout33 14 vout34 15 vout35 16 siggnd4 17 vout36 18 vout37 19 v dd 20 v ss 11 vout31 59 58 57 54 55 56 60 53 52 nc siggnd0 vout3 vout0 vout1 vout2 vout4 nc vref0 51 nc 49 vout23 48 vout22 47 vout21 46 vout20 45 v ss 44 v dd 43 nc 42 nc 41 siggnd2 50 vref2 nc = no connect 21 vref1 22 nc 23 nc 24 nc 25 vout38 26 vout39 27 vout8 28 vout9 29 vout10 30 vout11 31 siggnd1 32 vout12 33 vout13 34 vout14 35 nc 36 vout15 37 vout16 38 vout17 39 vout18 40 vout19 80 vout26 79 vout25 78 vout24 77 agnd 76 dgnd 75 dv cc 74 sdo 73 testo 72 spi/lvds 71 sdi 70 sdi 69 sclk 68 sclk 67 sync 66 sync 65 dv cc 64 dgnd 63 vout7 62 vout6 61 vout5 pin 1 ad5371 top view (not to scale) ldac 05814-007 figure 7. 80-lead l qfp pin configuration
ad5371 rev. b | page 11 of 28 dgnd v dd siggnd2 vout20 vout21 vout23 vref0 vout0 vout1 vout3 vout4 vout6 dgnd vout18 v dd vout19 vout22 vref2 nc nc vout2 siggnd0 vout5 vout7 dv cc vout16 vout17 dv cc sync vout14 vout15 v dd agnd agnd agnd agnd agnd sync sclk vout12 vout13 v dd agnd sclk sdi vout11 siggnd1 v dd agnd sdi spi/ lvds vout9 vout10 v dd agnd nc testo vout39 vout8 v dd agnd sdo ldac vref1 vout38 v ss v ss v ss v ss v ss agnd reset clr vout37 siggnd4 busy nc vout36 v ss vout34 vout32 vout30 vout28 nc vout24 vout25 agnd testi agnd 121110987654321 v ss vout35 vout33 vout31 vout29 nc siggnd3 vout27 vout26 agnd agnd a m l k j h g f e d c b 05814-025 figure 8. 100-ball grid array pin configurationbottom view table 7. pin function descriptions pin no. ball no. mnemonic description 1 a4 ldac load dac logic input (active low). see the busy and ldac functions section for more information. 2 a3 clr asynchronous clear input (level sensitive, active low). see the clear function section for more information. 3 b4 reset digital reset input. 4 b3 busy digital input/open-drain output . busy is open drain when an output. see the busy and ldac functions section for more information. 5 b2 testi test input pin. connect this pin to dgnd. 73 a5 testo test output pin. this pin remains unconnected. 54 to 57, 60 to 63, 27 to 30, 32 to 34, 36 to 40, 46 to 49, 78 to 80, 6, 8 to 15, 17, 18, 25, 26 f12, e12, e11, d12, c12, c11, b12, b11, l5, m6, l6, m7, m8, l8, m9, l9, m10, l10, m11, k11, k12, j12, j11, h12, e2, d2, d1, e1, g2, h1, h2, j1, j2, k1, k2, l1, m2, m3, l4, m5 vout0 to vout39 dac outputs. buffered analog outputs for each of the 40 dac channels. each analog output is capable of driving an output load of 10 k to ground. typical output impedance of these amplifiers is 0.5 .
ad5371 rev. b | page 12 of 28 pin no. ball no. mnemonic description 58 d11 siggnd0 reference ground for dac 0 to dac 7. vout0 to vout7 are referenced to this voltage. 31 l7 siggnd1 reference ground for dac 8 to dac 15. vout8 to vout15 are referenced to this voltage. 41 l12 siggnd2 reference ground for dac 16 to dac 23. vout16 to vout23 are referenced to this voltage. 7 f1 siggnd3 reference ground for dac 24 to dac 31. vout24 to vout31 are referenced to this voltage. 16 l3 siggnd4 reference ground for dac 32 to dac 39. vout32 to vout39 are referenced to this voltage. 52 g12 vref0 reference input for dac 0 to dac 7. this reference voltage is referred to agnd. 21 m4 vref1 reference input for dac 8 to dac 15. this reference voltage is referred to agnd. 50 h11 vref2 reference input for dac 16 to dac 39. this reference voltage is referred to agnd. 19, 44 j5 to j9, l11, m12 v dd positive analog power supply; 9 v to 16.5 v for specified performance. decouple these pins with 0.1 f ceramic capacitors and 10 f capacitors. 20, 45 e4, f4, g4, h4, j4, l2, m1 v ss negative analog power supply; ?16.5 v to ?8 v for specified performance. decouple these pins with 0.1 f ceramic capacitors and 10 f capacitors. 64, 76 a11, a12 dgnd ground for all digital circuitry. connect both dgnd pins to the dgnd plane. 65, 75 a10, b10 dv cc logic power supply; 2.5 v to 5.5 v. decouple th ese pins with 0.1 f ceramic capacitors and 10 f capacitors. 66 a9 sync active low or differential sync input (complement) for spi or lvds interface. this is the frame synchronization signal for the spi or lvds serial interface. see the timing characteristics section for more details. 67 b9 sync differential sync input for lvds interface. th is is the frame synchronization signal for the lvds serial interface. see the timing characteristics section for more details. 68 a8 sclk serial clock input for spi or lvds interface. see the timing characteristics section for more details. 69 b8 sclk differential serial clock input (complement) for lvds interface. see the timing characteristics section for more details. 70 a7 sdi serial data input for spi or lvds interface. see the timing characteristics section for more details. 71 b7 sdi differential serial data input (compl ement) for lvds interface. see the timing characteristics section for more details. 72 a6 spi /lvds interface selection pin. if the pin is low, the spi interface is selected. if the pin is high, the lvds interface is selected. 74 b5 sdo serial data output for spi interface. cmos o utput. sdo can be used for readback. data is clocked out on sdo on the rising edge of sclk and is valid on the falling edge of sclk. 77 a1, b1, c1, c2, d4 to d9, e9, f9, g9, h9 agnd ground for all analog circuitry. connect the agnd pin to the agnd plane. 22 to 24, 35, 42, 43, 51, 53, 59 a2, b6, f2, f11, g1, g11 nc no connect. do not connect these pins.
ad5371 rev. b | page 13 of 28 typical performance characteristics ?0.50 0.50 16383 dac code 0 0.25 0 ?0.25 4096 8192 12288 inl (lsb) 05814-009 figure 9. typical inl plot 7 6 5 4 3 2 1 0 number of units inl (lsb) v dd = +15v v ss = ?15v t a = 25c ?0.6 ?0.3 0 0.3 0.6 05814-010 figure 10. typical inl distribution ?1.0 ?0.5 0 0.5 1.0 inl error (lsb) v dd = +15v v ss = ?15v dv cc = +5v vref = +3v 80 60 40 20 0 temperature (c) 05814-011 figure 11. typical inl error vs. temperature ?0.02 ?0.01 0 amplitude (v) 02468 time (s) 1 0 t a = 25c v ss = ?15v v dd = +15v vref = +4.096v 05814-012 figure 12. analog crosstalk due to ldac ?0.0050 0 0.0050 amplitude (v) 012345 time (s) ?0.0025 0.0025 t a = 25c v ss = ?15v v dd = +15v vref = +4.096v 05814-013 figure 13. digital crosstalk ?1.0 1.0 16383 dac code 0 0.5 0 ?0.5 4096 8192 12288 dnl (lsb) 05814-014 figure 14. typical dnl plot
ad5371 rev. b | page 14 of 28 0 600 100 400 500 200 output noise (nv/ hz) 01234 5 300 frequency (hz) 05814-015 figure 15. output noise spectral density 0.25 0.30 0.35 0.40 0.45 0.50 di cc (ma) ?40?200 20406080 temperature (c) v ss = ?12v v dd = +12v vref = +3v dv cc = +5.5v dv cc = +3.6v dv cc = +2.5v 05814-016 figure 16. di cc vs. temperature 12.0 12.5 13.0 13.5 14.0 i dd /i ss ( |ma| ) ?40?200 20406080 temperature (c) v ss = ?12v v dd = +12v vref = +3v i ss i dd 05814-017 figure 17. i dd /i ss vs. temperature 14 12 10 8 6 4 2 0 number of units 14.00 13.75 13.50 13.25 13.00 i dd (ma) v ss = ?15v v dd = +15v t a = 25c 05814-018 figure 18. typical i dd distribution 14 12 10 8 6 4 2 0 number of units 0.50 0.45 0.40 0.35 0.30 di cc (ma) dv cc = 5v t a = 25c 05814-019 figure 19. typical di cc distribution
ad5371 rev. b | page 15 of 28 terminology integral nonlinearity (inl) integral nonlinearity, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (lsb). differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac register. zero-scale error is a measure of the difference between vout (actual) and vout (ideal), expressed in millivolts (mv), when the channel is at its minimum value. zero-scale error is mainly due to offsets in the output amplifier. full-scale error full-scale error is the error in the dac output voltage when all 1s are loaded into the dac register. full-scale error is a measure of the difference between vout (actual) and vout (ideal), expressed in millivolts, when the channel is at its maximum value. full-scale error does not include zero-scale error. gain error gain error is the difference between full-scale error and zero-scale error. it is expressed as a percentage of the full- scale range (fsr). gain error = full-scale error ? zero-scale error vout temperature coefficient the vout temperature coefficient includes output error contributions from linearity, offset, and gain drift. dc output impedance dc output impedance is the effective output source resistance. it is dominated by package lead resistance. dc crosstalk the dac outputs are buffered by op amps that share common v dd and v ss power supplies. if the dc load current changes in one channel (due to an update), this change can result in a further dc change in one or more channel outputs. this effect is more significant at high load currents and is reduced as the load currents are reduced. with high impedance loads, the effect is virtually immeasurable. multiple v dd and v ss terminals are provided to minimize dc crosstalk. output voltage settling time output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a full-scale input change. digital-to-analog glitch energy digital-to-analog glitch energy is the amount of energy that is injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-s. it is measured by toggling the dac register data between 0x1fff and 0x2000. channel-to-channel isolation channel-to-channel isolation refers to the proportion of input signal from the reference input of one dac that appears at the output of another dac operating from another reference. it is expressed in decibels and measured at midscale. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter. it is specified in nv-s. digital crosstalk digital crosstalk is defined as the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter. it is specified in nv-s. digital feedthrough when the device is not selected, high frequency logic activity on the digital inputs of the device can be capacitively coupled both across and through the device to appear as noise on the voutx pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. output noise spectral density output noise spectral density is a measure of internally gener- ated random noise. random noise is characterized as a spectral density (voltage per hz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/hz.
ad5371 rev. b | page 16 of 28 theory of operation dac architecture the ad5371 contains 40 dac channels and 40 output amplifiers in a single package. the architecture of a single dac channel consists of a 14-bit resistor-string dac followed by an output buffer amplifier. the resistor-string section is simply a string of resistors, of equal value, from vrefx to agnd. this type of architecture guarantees dac monotonicity. the 14-bit binary digital code loaded to the dac register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. the output amplifier multiplies the dac output voltage by 4. the nominal output span is 12 v with a 3 v reference and 20 v with a 5 v reference. channel groups the 40 dac channels of the ad5371 are arranged into five groups of eight channels. the eight dacs of group 0 derive their reference voltage from vref0. the eight dacs of group 1 derive their reference voltage from vref1. group 2 to group 4 derive their reference voltage from vref2. each group has its own signal ground pin. table 8. register descriptions register name word length (bits) default value description x1a 14 0x1555 input data register a. one for each dac channel. x1b 14 0x1555 input data register b. one for each dac channel. m 14 0x3fff gain trim registers. one for each dac channel. c 14 0x2000 offset trim registers. one for each dac channel. x2a 14 not user accessible output data register a. one for each dac channel. these registers store the final, calibrated dac data after gain and offset trimming. they are not readable or directly writable. x2b 14 not user accessible output data register b. one for each dac channel. these registers store the final, calibrated dac data after gain and offset trimming. they are not readable or directly writable. dac not user accessible data registers from which the dacs take their fi nal input data. the dac registers are updated from the x2a or x2b register. they are not readable or directly writable. ofs0 14 0x1555 offset dac 0 data register. sets offset for group 0. ofs1 14 0x1555 offset dac 1 data register. sets offset for group 1. ofs2 14 0x1555 offset dac 2 data register. sets offset for group 2 to group 4. control 3 0x00 bit 2 = a /b. 0 = global selection of x1a input data registers. 1 = global selection of x1b input data registers. bit 1 = enable thermal shutdown. 0 = disable thermal shutdown. 1 = enable thermal shutdown. bit 0 = software power-down. 0 = software power-up. 1 = software power-down. a/b select 0 8 0x00 each bit in this register determines if a dac in group 0 takes its data from register x2a or register x2b. 0 = x2a. 1 = x2b. a/b select 1 8 0x00 each bit in this register determines if a da c in group 1 takes its data from register x2a or register x2b. 0 = x2a. 1 = x2b. a/b select 2 8 0x00 each bit in this register determines if a da c in group 2 takes its data from register x2a or register x2b. 0 = x2a. 1 = x2b. a/b select 3 8 0x00 each bit in this register determines if a da c in group 3 takes its data from register x2a or register x2b. 0 = x2a. 1 = x2b. a/b select 4 8 0x00 each bit in this register determines if a da c in group 4 takes its data from register x2a or register x2b. 0 = x2a. 1 = x2b.
ad5371 rev. b | page 17 of 28 a/b registers and gain/offset adjustment each dac channel has seven data registers. the actual dac data-word can be written to either the x1a or the x1b input register, depending on the setting of the a /b bit in the control register. if the a /b bit is 0, data is written to the x1a register. if the a /b bit is 1, data is written to the x1b register. note that this single bit is a global control and affects every dac channel in the device. it is not possible to set up the device on a per- channel basis so that some writes are to x1a registers and some writes are to x1b registers. mux dac dac register mux x1a register x1b register m register c register x2a register x2b register 05814-020 figure 20. data registers associated with each dac channel each dac channel also has a gain (m) register and an offset (c) register that allow trimming out of the gain and offset errors of the entire signal chain. data from the x1a register is operated on by a digital multiplier and adder controlled by the contents of the m and c registers. the calibrated dac data is then stored in the x2a register. similarly, data from the x1b register is operated on by the multiplier and adder and stored in the x2b register. although figure 20 shows a multiplier and adder for each channel, there is only one multiplier and one adder in the device shared among all channels. this has implications for the update speed when several channels are updated simultaneously, as described in the register update rates section. each time data is written to the x1a register, or to the m or c register with the a /b control bit set to 0, the x2a data is recal- culated and the x2a register is automatically updated. similarly, x2b is updated each time data is written to x1b, or to m or c with a /b set to 1. the x2a and x2b registers are not readable or directly writable by the user. data output from the x2a and x2b registers is routed to the final dac register by a multiplexer. whether each individual dac takes its data from the x2a or x2b register is controlled by an 8-bit a/b select register associated with each group of eight dacs. if a bit in this register is 0, the dac takes its data from the x2a register; if 1, the dac takes its data from the x2b register (bit 0 through bit 7 control dac 0 to dac 7). note that because there are 40 bits in five registers, it is possible to set up, on a per-channel basis, whether each dac takes its data from the x2a or x2b register. a global command is also provided that sets all bits in the a/b select registers to 0 or to 1. load dac all dacs in the ad5371 can be updated simultaneously by taking ldac low when each dac register is updated from either its x2a or x2b register, depending on the setting of the a/b select registers. the dac register is not readable or directly writable by the user. ldac can be permanently tied low, and the dac output is updated whenever new data appears in the appropriate dac register. offset dacs in addition to the gain and offset trim for each dac, there are three 14-bit offset dacs, one for group 0, one for group 1, and one for group 2 to group 4. these allow the output range of all dacs connected to them to be offset within a defined range. thus, subject to the limitations of headroom, it is possible to set the output range of group 0, group 1, or group 2 to group 4 to be unipolar positive, unipolar negative, or bipolar, either symmet- rical or asymmetrical about 0 v. the dacs in the ad5371 are factory trimmed with the offset dacs set at their default values. this results in optimum offset and gain performance for the default output range and span. when the output range is adjusted by changing the value of the offset dac, an extra offset is introduced due to the gain error of the offset dac. the amount of offset is dependent on the magni- tude of the reference and how much the offset dac deviates from its default value. see the specifications section for this offset. the worst-case offset occurs when the offset dac is at positive or negative full scale. this value can be added to the offset present in the main dac channel to give an indication of the overall offset for that channel. in most cases, the offset can be removed by programming the c register of the channel with an appropriate value. the extra offset caused by the offset dac needs to be taken into account only when the offset dac is changed from its default value. figure 21 shows the allowable code range that can be loaded to the offset dac, depending on the reference value used. thus, for a 5 v reference, the offset dac should not be programmed with a value greater than 8192 (0x2000). 0 4096 8192 12288 16383 offset dac code 0 1 2 3 4 v r e f ( v ) 5 reserved 05814-021 figure 21. offset dac code range
ad5371 rev. b | page 18 of 28 output amplifier the output amplifiers can swing to 1.4 v below the positive supply and 1.4 v above the negative supply, which limits how much the output can be offset for a given reference voltage. for example, it is not possible to have a unipolar output range of 20 v, because the maximum supply voltage is 16.5 v. clr clr clr dac channel offset dac v out r6 10k ? r2 20k ? s3 s2 s1 r4 60k ? r3 20k ? siggndx siggndx r5 60k ? r1 20k ? 05814-022 figure 22. output ampl ifier and offset dac figure 22 shows details of a dac output amplifier and its connections to its corresponding offset dac. on power-up, s1 is open, disconnecting the amplifier from the output. s3 is closed, so the output is pulled to the corresponding siggndx (r1 and r2 are greater than r6). s2 is also closed to prevent the output amplifier from being open-loop. if clr is low at power-up, the output remains in this condition until clr is taken high. the dac registers can be programmed, and the outputs assume the programmed values when clr is taken high. even if clr is high at power-up, the output remains in this condition until v dd > 6 v and v ss < ?4 v and the initialization sequence has finished. the outputs then go to their power-on default value. transfer function dac code full-scale error + zero-scale error zero-scale error ?4v 0 16383 8v ideal transfer function actual transfer function output voltage 05814-008 figure 23. dac transfer function the output voltage of a dac in the ad5371 is dependent on the value in the input register, the value of the m and c registers, and the value in the offset dac. the input code is the value in the x1a or x1b register that is applied to the dac (x1a, x1b default code = 5461). dac_code = input_code ( m + 1)/2 14 + c ? 2 13 . where: m = code in gain register ? default code = 2 14 ? 1. c = code in offset register ? default code = 2 13 . the dac output voltage is calculated as follows: vout = 4 vrefx ( dac_code C offset_code )/2 14 + v siggnd where: dac_code should be within the range of 0 to 16,383. vref = 3.0 v for a 12 v span and 5.0 v for a 20 v span. offset_code is the code loaded to the offset dac. on power-up, the default code loaded to the offset dac is 5461 (0x1555). with a 3 v reference, this gives a span of ?4 v to +8 v. reference selection the ad5371 has three reference input pins. the voltage applied to the reference pins determines the output voltage span on vout0 to vout39. vref0 determines the voltage span for vout0 to vout7 (group 0), vref1 determines the voltage span for vout8 to vout15 (group 1), and vref2 deter- mines the voltage span for vout16 to vout39 (group 2 to group 4). the reference voltage applied to each vref pin can be different, if required, allowing each group to have a different voltage span. the output voltage range and span can be adjusted further by programming the offset and gain registers for each channel and by programming the offset dacs. if the offset and gain features are not used (that is, the m and c registers are left at their default values), the required reference levels can be calculated as follows: vref = ( vout max ? vout min )/4 if the offset and gain features of the ad5371 are used, the required output range is slightly different. the selected output range should take into account the system offset and gain errors that need to be trimmed out. therefore, the selected output range should be larger than the actual required range. calculate the required reference levels as follows: 1. identify the nominal output range on vout. 2. identify the maximum offset span and the maximum gain required on the full output signal range. 3. calculate the new maximum output range on vout, including the expected maximum offset and gain errors. 4. choose the new required vout max and vout min , keeping the vout limits centered on the nominal values. note that v dd and v ss must provide sufficient headroom. 5. calculate the value of vref as follows: vref = ( vout max ? vout min )/4
ad5371 rev. b | page 19 of 28 reference selection example if nominal output range = 12 v (?4 v to +8 v) zero-scale error = 70 mv gain error = 3%, and siggndx = agnd = 0 v then gain error = 3% => maximum positive gain error = 3% => output range including gain error = 12 + 0.03(12) = 12.36 v zero-scale error = 70 mv => maximum offset error span = 2(70 mv) = 0.14 v => output range including gain error and zero-scale error = 12.36 v + 0.14 v = 12.5 v vref calculation actual output range = 12.5 v, that is, ?4.25 v to +8.25 v; vref = (8.25 v + 4.25 v)/4 = 3.125 v if the solution yields an inconvenient reference level, the user can adopt one of the following approaches: ? use a resistor divider to divide down a convenient, higher reference level to the required level. ? select a convenient reference level above vref and modify the gain and offset registers to digitally downsize the reference. in this way, the user can use almost any convenient reference level but can reduce the performance by overcompaction of the transfer function. ? use a combination of these two approaches. calibration the user can perform a system calibration on the ad5371 to reduce gain and offset errors to below 1 lsb. this reduction is achieved by calculating new values for the m and c registers and reprogramming them. the m and c registers should not be programmed until both the zero-scale and full-scale errors are calculated. reducing zero-scale error zero-scale error can be reduced as follows: 1. set the output to the lowest possible value. 2. measure the actual output voltage and compare it to the required value. this gives the zero-scale error. 3. calculate the number of lsbs equivalent to the error and add this number to the default value of the c register. note that only negative zero-scale error can be reduced. reducing full-scale error full-scale error can be reduced as follows: 1. measure the zero-scale error. 2. set the output to the highest possible value. 3. measure the actual output voltage and compare it to the required value. add this error to the zero-scale error. this is the span error, which includes the full-scale error. 4. calculate the number of lsbs equivalent to the span error and subtract this number from the default value of the m register. note that only positive full-scale error can be reduced. ad5371 calibration example this example assumes that a ?4 v to +8 v output is required. the dac output is set to ?4 v but measured at ?4.03 v. this gives a zero-scale error of ?30 mv. 1 lsb = 12 v/16,384 = 732.42 v 30 mv = 41 lsbs the full-scale error can now be calculated. the output is set to 8 v and a value of 8.02 v is measured. this gives a full-scale error of +20 mv and a span error of +20 mv ? (?30 mv) = +50 mv. 50 mv = 68 lsbs the errors can now be removed as follows: 1. add 41 lsbs to the default c register value: 8192 + 41 = 8233 2. subtract 68 lsbs from the default m register value: 16,383 ? 68 = 16,315 3. program the m register to 16,315; program the c register to 8233. additional calibration the techniques described in the previous section are usually enough to reduce the zero-scale and full-scale errors in most applications. however, there are limitations whereby the errors may not be sufficiently reduced. for example, the offset (c) register can only be used to reduce the offset caused by the negative zero-scale error. a positive offset cannot be reduced. likewise, if the maximum voltage is below the ideal value, that is, a negative full-scale error, the gain (m) register cannot be used to increase the gain to compensate for the error. these limitations can be overcome by increasing the reference value. with a 3 v reference, a 12 v span is achieved. the ideal voltage range for the ad5371 is ?4 v to +8 v. using a +3.1 v reference increases the range to ?4.133 v to +8.2667 v. clearly, in this case, the offset and gain errors are insignificant, and the m and c registers can be used to raise the negative voltage to ?4 v and then reduce the maximum voltage to +8 v to give the most accurate values possible.
ad5371 rev. b | page 20 of 28 reset function the reset function is initiated by the reset pin. on the rising edge of reset , the ad5371 state machine initiates a reset sequence to reset the x, m, and c registers to their default values. this sequence typically takes 300 s, and the user should not write to the part during this time. on power-up, it is recom- mended that the user bring reset high as soon as possible to properly initialize the registers. when the reset sequence is complete (and provided that clr is high), the dac output is at a potential specified by the default register settings, which is equivalent to siggndx. the dac outputs remain at siggndx until the x, m, or c register is updated and ldac is taken low. the ad5371 can be returned to the default state by pulsing reset low for at least 30 ns. note that, because the reset function is triggered by the rising edge, bringing reset low has no effect on the operation of the ad5371. clear function clr is an active low input that should be high for normal oper- ation. the clr pin has an internal 500 k pull-down resistor. when clr is low, the input to each of the dac output buffer stages, vout0 to vout39, is switched to the externally set potential on the relevant siggndx pin. while clr is low, all ldac pulses are ignored. when clr is taken high again, the dac outputs return to their previous values. the contents of the input registers and the dac registers are not affected by taking clr low. to prevent glitches from appearing on the outputs, bring clr low before writing to the offset dac to adjust the output span. busy and ldac functions the value of an x2 (a or b) register is calculated each time the user writes new data to the corresponding x1, c, or m register. during the calculation of x2, the busy output goes low. while busy is low, the user can continue writing new data to the x1, m, or c register (see the register update rates section for more details), but no dac output updates can take place. the busy pin is bidirectional and has a 50 k internal pull-up resistor. when multiple ad5371 devices are used in one system, the busy pins can be tied together. this is useful when it is required that no dac in any device be updated until all other dacs are ready to be updated. when each device has finished updating the x2 (a or b) register, it releases the busy pin. if another device has not finished updating its x2 register, it holds busy low, thus delaying the effect of ldac going low. the dac outputs are updated by taking the ldac input low. if ldac goes low while busy is active, the ldac event is stored and the dac outputs are updated immediately after busy goes high. a user can also hold the ldac input permanently low. in this case, the dac outputs are updated immediately after busy goes high. whenever the a/b select registers are written to, busy also goes low for approximately 500 ns. the ad5371 has flexible addressing that allows writing of data to a single channel, all channels in a group, the same channel in group 0 to group 4, the same channel in group 1 to group 4, or all channels in the device. this means that 1, 4, 5, 8, or 40 dac register values may need to be calculated and updated. because there is only one multiplier shared among 40 channels, this task must be done sequentially so that the length of the busy pulse varies according to the number of channels being updated. table 9. busy pulse widths action busy pulse width 1 loading x1a, x1b, c, or m to 1 channel 2 1.5 s maximum loading x1a, x1b, c, or m to 5 channels 3.9 s maximum loading x1a, x1b, c, or m to 8 channels 5.7 s maximum loading x1a, x1b, c, or m to 40 channels 24.9 s maximum 1 busy pulse width = ((number of cha nnels + 1) 600 ns) + 300 ns. 2 a single channel update is typically 1 s. the ad5371 contains an extra feature whereby a dac register is not updated unless its x2a or x2b register has been written to since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the x2a or x2b register, depending on the setting of the a/b select registers. however, the ad5371 updates the dac register only if the x2a or x2b data has changed, thereby removing unnecessary digital crosstalk. power-down mode the ad5371 can be powered down by setting bit 0 in the control register to 1. this turns off the dacs, thus reducing the current consumption. the dac outputs are connected to their respective siggndx potentials. the power-down mode does not change the contents of the registers, and the dacs return to their previous voltage when the power-down bit is cleared to 0. thermal shutdown function the ad5371 can be programmed to shut down the dacs if the temperature on the die exceeds 130c. setting bit 1 in the control register to 1 enables this function (see table 17 ). if the die temperature exceeds 130c, the ad5371 enters a thermal shutdown mode that is equivalent to setting the power-down bit in the control register to 1. to indicate that the ad5371 has entered thermal shutdown mode, bit 4 of the control register is set to 1. the ad5371 remains in thermal shutdown mode, even if the die temperature falls, until bit 1 in the control register is cleared to 0.
ad5371 rev. b | page 21 of 28 toggle mode the ad5371 has two x2 registers per channel, x2a and x2b, that can be used to switch the dac output between two levels with ease. this approach greatly reduces the overhead required by a microprocessor, which would otherwise need to write to each channel individually. when the user writes to the x1a, x1b, m, or c register, the calculation engine takes a certain amount of time to calculate the appropriate x2a or x2b value. if an application, such as a data generator, requires that the dac output switch between two levels only, any method that reduces the amount of calculation time necessary is advantageous. for the data generator example, the user needs only to set the high and low levels for each channel once by writing to the x1a and x1b registers. the values of x2a and x2b are calculated and stored in their respective registers. the calculation delay, therefore, happens only during the setup phase, that is, when programming the initial values. to toggle a dac output between the two levels, it is only required to write to the relevant a/b select register to set the mux2 register bit. furthermore, because there are eight mux2 control bits per register, it is possible to update eight channels with a single write. table 10 shows the bits that corre- spond to each dac output. table 10. dacs selected by a/b select registers bits 1 a/b select register f7 f6 f5 f4 f3 f2 f1 f0 0 vout7 vout6 vout5 vout4 vout3 vout2 vout1 vout0 1 vout15 vout14 vout13 vout12 vout11 vout10 vout9 vout8 2 vout23 vout22 vout21 vout20 vout19 vout18 vout17 vout16 3 vout31 vout30 vout29 vout28 vout27 vout26 vout25 vout24 4 vout39 vout38 vout37 vout36 vout35 vout34 vout33 vout32 1 if the bit is set to 0, register x2a is selected. if the bit is set to 1, register x2b is selected.
ad5371 rev. b | page 22 of 28 serial interface the ad5371 contains two high speed serial interfaces: an spi- compatible interface operating at clock frequencies up to 50 mhz (20 mhz for read operations) and an lvds interface. to minimize both the power consumption of the device and the on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of sync . spi interface the serial interface is 2.5 v lvttl-compatible when operating from a 2.5 v to 3.6 v dv cc supply. the spi interface is selected when the spi /lvds pin is held low. it is controlled by four pins, as described in table 11 . table 11. pins that control the spi interface pin description sync frame synchronization input sdi serial data input pin sclk clocks data in and out of the device sdo serial data output pin for data readback when the spi mode is used, the sync, sdi , and sclk pins should be connected to dgnd either directly or by using pull- down resistors. lvds interface the lvds interface uses the same input pins, with the same designations, as the spi interface; however, sdo is not used. in addition, three other pins are provided for the complementary signals needed for differential operation, as described in table 12 . table 12. pins that control the lvds interface pin description sync differential frame synchronization signal sync differential frame synchronization signal (complement) sdi differential serial data input sdi differential serial da ta input (complement) sclk differential serial clock input sclk differential serial clock input (complement) spi write mode the ad5371 allows writing of data via the serial interface to every register directly accessible to the serial interface, that is, all registers except the x2a, x2b, and dac registers. the x2a and x2b registers are updated when the user writes to the x1a, x1b, m, or c register, and the dac data registers are updated by ldac . the serial word (see table 13 ) is 24 bits long: 14 of these bits are data bits; six bits are address bits; two bits are mode bits that determine what is done with the data; and two bits are reserved. the serial interface works with both a continuous and a burst (gated) serial clock. serial data applied to sdi is clocked into the ad5371 by clock pulses applied to sclk. the first falling edge of sync starts the write cycle. at least 24 falling clock edges must be applied to sclk to clock in 24 bits of data before sync is taken high again. if sync is taken high before the 24 th falling clock edge, the write operation is aborted. if a continuous clock is used, sync must be taken high before the 25 th falling clock edge. this inhibits the clock within the ad5371. if more than 24 falling clock edges are applied before sync is taken high again, the input data becomes corrupted. if an externally gated clock of exactly 24 pulses is used, sync can be taken high any time after the 24 th falling clock edge. the input register addressed is updated on the rising edge of sync . for another serial transfer to take place, sync must be taken low again. table 13. serial word bit assignment i23 i22 i21 i20 i1 9 i18 i17 i16 i15 i14 i13 i12 i11 i1 0 i9 i8 i7 i6 i5 i4 i3 i2 i1 1 i0 1 m1 m0 a5 a4 a3 a2 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 bit i1 and bit i0 are reserved for future use and should be set to 0 when writing the serial word. these bits read back as 0.
ad5371 rev. b | page 23 of 28 spi readback mode the ad5371 allows data readback via the serial interface from every register directly accessible to the serial interface, that is, all registers except the x2a, x2b, and dac data registers. to read back a register, it is first necessary to tell the ad5371 which register is to be read. this is achieved by writing a word whose first two bits are the special function code 00 to the device. the remaining bits then determine which register is to be read back. if a readback command is written to a special function register, data from the selected register is clocked out of the sdo pin during the next spi operation. the sdo pin is normally three- stated but becomes driven as soon as a read command is issued. the pin remains driven until the register data is clocked out. see figure 5 for the read timing diagram. note that due to the timing requirements of t 22 (25 ns), the maximum speed of the spi interface during a read operation should not exceed 20 mhz. lvds operation the lvds interface operates as follows. note that, because the lvds signals are differential, when a signal goes high, its complementary signal goes low, and vice versa. 1. the sync signal frames the data. sclk is initially high. 2. after sync goes high and the sync -to-sclk setup time has elapsed, sclk can start to clock in the data. 3. data is clocked into the ad5371 on the high-to-low transition of sclk and must be stable at this time (observe setup and hold time specifications). 4. sync can then be taken low after the sclk-to- sync hold time to latch the data. the same comments about burst and continuous clocks for the spi interface apply to the lvds interface. however, readback is not available when using the lvds interface. register update rates the value of the x2a register or the x2b register is calculated each time the user writes new data to the corresponding x1, c, or m register. the calculation is performed by a three-stage process. the first two stages take approximately 600 ns each, and the third stage takes approximately 300 ns. when the write to the x1, c, or m register is complete, the calculation process begins. if the write operation involves the update of a single dac channel, the user is free to write to another register, provided that the write operation does not finish until the first-stage calculation is complete, that is, 600 ns after the completion of the first write operation. if a group of channels is being updated by a single write operation, the first-stage calculation is repeated for each channel, taking 600 ns per channel. in this case, the user should not complete the next write operation until this time has elapsed. channel addressing and special modes if the mode bits are not 00, the data-word d13 to d0 is written to the device. address bit a5 to address bit a0 determine which channels are written to, and the mode bits determine to which register (x1a, x1b, c, or m) the data is written, as shown in table 14 and table 15 . data is to be written to the x1a register when the a /b bit in the control register is 0, or to the x1b register when the a /b bit is 1. table 14. mode bits m1 m0 action 1 1 write to dac input data (x) register 1 0 write to dac offset (c) register 0 1 write to dac gain (m) register 0 0 special function, used in combination with other bits of the data-word the ad5371 has very flexible addressing that allows the writing of data to a single channel, all channels in a group, the same channel in group 0 to group 4, the same channel in group 1 to group 4, or all channels in the device (see tabl e 15 ).
ad5371 rev. b | page 24 of 28 table 15 shows which groups and which channels are addressed for every combination of address bit a5 to address bit a0. table 15. group and channel addressing address bit a5 to address bit a3 address bit a2 to address bit a0 000 001 010 011 100 101 110 111 000 all groups, all channels group 0, channel 0 group 1, channel 0 group 2, channel 0 group 3, channel 0 group 4, channel 0 group 0, group 1, group 2, group 3, group 4; channel 0 group 1, group 2, group 3, group 4; channel 0 000 group 0, all channels group 0, channel 1 group 1, channel 1 group 2, channel 1 group 3, channel 1 group 4, channel 1 group 0, group 1, group 2, group 3, group 4; channel 1 group 1, group 2, group 3, group 4; channel 1 010 group 1, all channels group 0, channel 2 group 1, channel 2 group 2, channel 2 group 3, channel 2 group 4, channel 2 group 0, group 1, group 2, group 3, group 4; channel 2 group 1, group 2, group 3, group 4; channel 2 011 group 2, all channels group 0, channel 3 group 1, channel 3 group 2, channel 3 group 3, channel 3 group 4, channel 3 group 0, group 1, group 2, group 3, group 4; channel 3 group 1, group 2, group 3, group 4; channel 3 100 group 3, all channels group 0, channel 4 group 1, channel 4 group 2, channel 4 group 3, channel 4 group 4, channel 4 group 0, group 1, group 2, group 3, group 4; channel 4 group 1, group 2, group 3, group 4; channel 4 101 group 4, all channels group 0, channel 5 group 1, channel 5 group 2, channel 5 group 3, channel 5 group 4, channel 5 group 0, group 1, group 2, group 3, group 4; channel 5 group 1, group 2, group 3, group 4; channel 5 110 reserved group 0, channel 6 group 1, channel 6 group 2, channel 6 group 3, channel 6 group 4, channel 6 group 0, group 1, group 2, group 3, group 4; channel 6 group 1, group 2, group 3, group 4; channel 6 111 reserved group 0, channel 7 group 1, channel 7 group 2, channel 7 group 3, channel 7 group 4, channel 7 group 0, group 1, group 2, group 3, group 4; channel 7 group 1, group 2, group 3, group 4; channel 7
ad5371 rev. b | page 25 of 28 special function mode if the mode bits are 00, the special function mode is selected, as shown in table 16 . bit i21 to bit i16 of the serial data-word select the special function, and the remaining bits are data required for executio n of the special function, for example, the channel address for data readback. the codes for the special functions are shown in table 17 . table 18 shows the addresses for data readback. table 16. special function mode i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 0 0 s5 s4 s3 s2 s1 s0 f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 table 17. special function codes special function code s5 s4 s3 s2 s1 s0 data (f15 to f0) action 0 0 0 0 0 0 0000 0000 0000 0000 no operation (nop). 0 0 0 0 0 1 xxxx xxxx xxxx x[f2:f0] write control register. f4 = overtemperature indicator (read-only bit). this bit should be 0 when writing to the control register. f3 = reserved. this bit should be 0 when writing to the control register. f2 = 1: select register x1b for input. f2 = 0: select register x1a for input. f1 = 1: enable thermal shutdown mode. f1 = 0: disable thermal shutdown mode. f0 = 1: software power-down. f0 = 0: software power-up. 0 0 0 0 1 0 xx[f13:f0] write data in f13 to f0 to ofs0 register. 0 0 0 0 1 1 xx[f13:f0] write data in f13 to f0 to ofs1 register. 0 0 0 1 0 0 xx[f13:f0] write data in f13 to f0 to ofs2 register. 0 0 0 1 0 1 see table 18 select register for readback. 0 0 0 1 1 0 xxxx xxxx [f7:f0] write data in f7 to f0 to a/b select register 0. 0 0 0 1 1 1 xxxx xxxx [f7:f0] write data in f7 to f0 to a/b select register 1. 0 0 1 0 0 0 xxxx xxxx [f7:f0] write data in f7 to f0 to a/b select register 2. 0 0 1 0 0 1 xxxx xxxx [f7:f0] write data in f7 to f0 to a/b select register 3. 0 0 1 0 1 0 xxxx xxxx [f7:f0] write data in f7 to f0 to a/b select register 4. 0 0 1 0 1 1 xxxx xxxx [f7:f0] block write to a/b select registers. f7 to f0 = 0: write all 0s (all channels use the x2a register). f7 to f0 = 1: write all 1s (all channels use the x2b register). 0 1 1 1 0 0 reserved
ad5371 rev. b | page 26 of 28 table 18. address codes for data readback 1 f15 f14 f13 f12 f11 f10 f9 f8 f7 register read 0 0 0 x1a register 0 0 1 x1b register 0 1 0 c register 0 1 1 bit f12 to bit f7 select the channel to be read back, from channel 0 = 001000 to channel 39 = 101111 m register 1 0 0 0 0 0 0 0 1 control register 1 0 0 0 0 0 0 1 0 ofs0 data register 1 0 0 0 0 0 0 1 1 ofs1 data register 1 0 0 0 0 0 1 0 0 ofs2 data register 1 0 0 0 0 0 1 1 0 a/b select register 0 1 0 0 0 0 0 1 1 1 a/b select register 1 1 0 0 0 0 1 0 0 0 a/b select register 2 1 0 0 0 0 1 0 0 1 a/b select register 3 1 0 0 0 0 1 0 1 0 a/b select register 4 1 bit f6 to bit f0 are dont cares for the data readback function.
ad5371 rev. b | page 27 of 28 applications information power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. design the pcb on which the ad5371 is mounted so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5371 is in a system where multiple devices require an agnd-to-dgnd connection, make the connection at one point only. establish the star ground point as close as possible to the device. for supplies with multiple pins (v ss , v dd , dv cc ), it is recommended that these pins be tied together and that each supply be decoupled only once. the ad5371 should have ample supply decoupling of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi)typical of the common ceramic types that provide a low impedance path to ground at high frequenciesto handle transient currents due to internal logic switching. avoid digital lines running under the device because they can couple noise onto the device. allow the analog ground plane, however, to run under the ad5371 to avoid noise coupling. the power supply lines of the ad5371 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. shield fast switching digital signals with digital ground to avoid radiating noise to other parts of the board, and never run them near the reference inputs. it is essential to minimize noise on all vref lines. avoid crossover of digital and analog signals. run traces on opposite sides of the board at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best approach, but it is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. power supply sequencing when the supplies are connected to the ad5371, it is important that the agnd and dgnd pins be connected to the relevant ground plane before the positive or negative supplies are applied. in most applications, this is not an issue because the ground pins for the power supplies are connected to the ground pins of the ad5371 via ground planes. when the ad5371 is to be used in a hot-swap card, care should be taken to ensure that the ground pins are connected to the supply grounds before the positive or negative supplies are connected. this is required to prevent currents from flowing in directions other than toward an analog or digital ground. interfacing examples the spi interface of the ad5371 is designed to allow the part to be easily connected to industry-standard dsps and microcontrollers. figure 24 shows how the ad5371 connects to the analog devices, inc., blackfin? dsp. the blackfin has an integrated spi port that can be connected directly to the spi pins of the ad5371, as well as programmable input/output pins that can be used to set or read the state of the digital input or output pins associated with the interface. spiselx adsp-bf531 ad5371 sck mosi miso pf10 pf8 pf9 pf7 sync sclk sdi sdo reset clr ldac busy 05814-023 figure 24. interfacing to a blackfin dsp the analog devices adsp-21065l is a floating-point dsp with two serial ports (sports). figure 25 shows how one sport can be used to control the ad5371. in this example, the transmit frame synchronization (tfsx) pin is connected to the receive frame synchronization (rfsx) pin. similarly, the transmit and receive clocks (tclkx and rclkx) are also connected. the user can write to the ad5371 by writing to the transmit register of the adsp-21065l. a read operation can be accomplished by first writing to the ad5371 to tell the part that a read operation is required. a second write operation with an nop instruction causes the data to be read from the ad5371. the dsp receive interrupt can be used to indicate when the read operation is complete. sync sclk sdi sdo reset clr ldac busy ad5371 adsp-21065l tfsx rfsx tclkx rclkx dtxa drxa flag 0 flag 1 flag 2 flag 3 05814-024 figure 25. interfacing to an adsp-21065l dsp
ad5371 rev. b | page 28 of 28 outline dimensions compliant to jedec standards ms-026-bdd 051706-a 0.15 0.05 1.45 1.40 1.35 0.20 0.09 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 top view (pins down) 1 21 41 40 60 61 80 20 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a pin 1 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 figure 26. 80-lead low profile quad flat package [lqfp] st-80-1 dimensions shown in millimeters b c d e f g h j k l m a seating plane 0.34 nom 0.29 min detail a * 0.50 0.45 0.40 ball diameter 0.12 max coplanarity 0.80 bsc 8.80 bsc sq 12 11 109 87654321 a 1 corne r index area top view bottom view 10.00 bsc sq ball a1 pad corner detail a 2.50 sq 1.40 1.35 1.20 1.11 1.01 0.91 0.65 ref * compliant to jedec standards mo-205ac with the exception to ball diameter. 012006-0 figure 27. 100-ball chip scale package ball grid array [csp_bga] (bc-100-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad5371bstz 1 ?40c to +85c 80-lead low profile quad flat package [lqfp] st-80-1 AD5371BSTZ-REEL 1 ?40c to +85c 80-lead low profile quad flat package [lqfp] st-80-1 ad5371bbcz 1 ?40c to +85c 100-ball chip scale package ball grid array (csp_bga) bc-100-2 ad5371bbcz-reel 1 ?40c to +85c 100-ball chip scale package ball grid array (csp_bga) bc-100-2 eval-ad5371ebz 1 evaluation board 1 z = rohs compliant part. ?2007C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05814-0-3/08(b)

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